(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices such as metal oxide semiconductor field effect (MOSFET) devices, and more specifically to devices formed with strained channel regions.
(2) Description of Prior Art
Enhanced performance of MOSFET devices has been addressed via device channel regions formed in strained layers. Increased carrier mobility and thus enhanced device performance has been achieved in both P channel (PMOS) as well as N channel (NMOS) structures via formation of channel regions in strained layers. Formation of strained layers such as a strained silicon layer can be accomplished by formation of the silicon layer on an underlying substrate or layer comprised of silicon-germanium or silicon-germanium carbon.
The magnitude of strain as well as the type of strain, tensile or compressive, is a function of the level of germanium in the underlying materials. To achieve the desired properties of the strained layer the underlying material, such as a silicon-germanium layer or alike substrate, has to remain stable and undisturbed during subsequent device processing, therefore the integration of the silicon-germanium layer or alike substrate into a MOSFET device process sequence has to be carefully implemented.
The present invention will describe process integration sequences in which the critical silicon-germanium material layer is not adversely effected by subsequent MOSFET processing steps such as formation of shallow trench isolation (STI) elements, or high temperature anneal procedures. Prior art such as Chiu et al in U.S. Pat. No. 2004/0209437 A1, Koester et al in U.S. Pat. No. 2004/0164373 A1, Ngo et al in U.S. Pat. No. 2004/0137742 A1, Wang et al in U.S. Pat. No. 2004/0180509 A1, as well as Comfort et al in U.S. Pat. No. 5,308,785, describe methods of forming isolation structures in strained silicon and in underlying silicon-germanium layers. The above prior art however does not teach the process integration sequence of the present invention in which specific process sequences such as STI formation are integrated into a MOSFET process without adverse consequence of the strained and underlying layers.